The present invention is directed, in general, to processors and, more specifically, to a system and method for executing a three-operand instruction within the confines of a two-operand pipeline and a processor employing the same.
The ever-growing requirement for high performance computers demands that computer hardware architectures maximize software performance. Conventional computer architectures are made up of three primary components: (1) a processor, (2) a system memory and (3) one or more input/output devices. The processor controls the system memory and the input/output (xe2x80x9cI/Oxe2x80x9d) devices. The system memory stores not only data, but also instructions that the processor is capable of retrieving and executing to cause the computer to perform one or more desired processes or functions. The I/O devices are operative to interact with a user through a graphical user interface (xe2x80x9cGUIxe2x80x9d) (such as provided by Microsoft Windows(trademark) or IBM OS/2(trademark)), a network portal device, a printer, a mouse or other conventional device for facilitating interaction between the user and the computer.
Over the years, the quest for ever-increasing processing speeds has followed different directions. One approach to improve computer performance is to increase the rate of the clock that drives the processor. As the clock rate increases, however, the processor""s power consumption and temperature also increase. Increased power consumption is expensive and high circuit temperatures may damage the processor. Further, the processor clock rate may not increase beyond a threshold physical speed at which signals may traverse the processor. Simply stated, a practical maximum exists to the clock rate that is acceptable to conventional processors.
An alternate approach to improve computer performance is to increase the number of instructions executed per clock cycle by the processor (xe2x80x9cprocessor throughputxe2x80x9d). One technique for increasing processor throughput is pipelining, which calls for the processor to be divided into separate processing stages (collectively termed a xe2x80x9cpipelinexe2x80x9d). Instructions are processed in an xe2x80x9cassembly linexe2x80x9d fashion in the processing stages. Each processing stage is optimized to perform a particular processing function, thereby causing the processor as a whole to become faster.
xe2x80x9cSuperpipeliningxe2x80x9d extends the pipelining concept further by allowing the simultaneous processing of multiple instructions in the pipeline. Consider, as an example, a processor in which each instruction executes in six stages, each stage requiring a single clock cycle to perform its function. Six separate instructions can therefore be processed concurrently in the pipeline; i.e., the processing of one instruction is completed during each clock cycle. The instruction throughput of an n-stage pipelined architecture is therefore, in theory, n times greater than the throughput of a non-pipelined architecture capable of completing only one instruction every n clock cycles.
Another technique for increasing overall processor speed is xe2x80x9csuperscalarxe2x80x9d processing. Superscalar processing calls for multiple instructions to be processed per clock cycle. Assuming that instructions are independent of one another (the execution of each instruction does not depend upon the execution of any other instruction), processor throughput is increased in proportion to the number of instructions processed per clock cycle (xe2x80x9cdegree of scalabilityxe2x80x9d). If, for example, a particular processor architecture is superscalar to degree three (i.e., three instructions are processed during each clock cycle), the instruction throughput of the processor is theoretically tripled.
These techniques are not mutually exclusive; processors may be both superpipelined and superscalar. However, operation of such processors in practice is often far from ideal, as instructions tend to depend upon one another and are also often not executed efficiently within the pipeline stages. In actual operation, instructions often require varying amounts of processor resources, creating interruptions (xe2x80x9cbubblesxe2x80x9d or xe2x80x9cstallsxe2x80x9d) in the flow of instructions through the pipeline. Consequently, while superpipelining and superscalar techniques do increase throughput, the actual throughput of the processor ultimately depends upon the particular instructions processed during a given period of time and the particular implementation of the processor""s architecture.
The speed at which a processor can perform a desired task is also a function of the number of instructions required to code the task. A processor may require one or many clock cycles to execute a particular instruction. Thus, in order to enhance the speed at which a processor can perform a desired task, both the number of instructions used to code the task as well as the number of clock cycles required to execute each instruction should be minimized.
Statistically, certain instructions are executed more frequently than others. If the design of a processor is optimized to rapidly process the instructions which occur most frequently, then the overall throughput of the processor can be increased. Unfortunately, the optimization of a processor for certain frequent instructions is usually obtained only at the expense of other less frequent instructions, or requires additional circuitry, which increases the size of the processor.
One area in which less frequent instructions have dictated a compromise in design is in the area of multiple-operand processing. For each operand of an instruction, a portion of a bus must be used to pass the operand from a reservation station to an execution unit. For example, in 32 bit microprocessor architectures that have three operand instructions, the microprocessor uses three 32 bit buses to pass the instruction""s three operands from the reservation station to the execution unit. The most common instructions that contain three or more operands are the multiply and the divide instructions.
Microprocessors use multiple operand buses to reduce the time required to process these less frequent instructions. However, the additional circuitry required to implement theses additional buses increase the size of the processor and increase the processor""s power usage. Therefore, what is needed in the art is a way to process multiple-operand instructions without the cost of additional operand buses.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a way to execute instructions that have more operands than the pipeline can convey in parallel.
In the attainment of the above primary object, the present invention provides, for use in a processor having a pipeline of insufficient width to convey all operands of a given multiple-operand instruction concurrently, a system for, and method of, processing the multiple-operand instruction. In one embodiment, the system includes: (1) node creation circuitry that creates at least first and second nodes for the multiple-operand instruction, the first node being empty and containing at least one of the operands and (2) node transmission circuitry, coupled to the node creation circuitry, that transmits the first and second nodes sequentially through the pipeline. All the operands are subsequently concurrently available within an execution stage of the pipeline for execution of the multiple-operand instruction.
The present invention introduces the broad concept of employing empty nodes (nodes that the execution unit ignores and therefore does not execute) to convey one or more of the operands of a multi-operand instruction. This allows the bus within the pipeline to convey more operands for a given instruction than could be otherwise conveyed were all the operands to be conveyed with the instruction itself.
In one embodiment of the present invention, the pipeline has a width sufficient to convey two operands. However, the broad scope of the present invention contemplates pipelines capable of conveying one or more operands in parallel.
In one embodiment of the present invention, the multiple-operand instruction is a three-operand instruction. Those skilled in the pertinent art will understand, however, that the present invention broadly applies to instructions having two or more operands, as long as the pipeline is narrower than the number of operands.
In one embodiment of the present invention, the node transmission circuitry is contained within a reservation station associated with the pipeline. In an embodiment to be illustrated and described, the processor contains three pipelines and three corresponding reservation stations. Each of the reservation stations has node creation circuitry and node transmission circuitry.
In one embodiment of the present invention, the node transmission circuitry transmits the first node before the second node. The execution unit holds the operand(s) transmitted with the first node until the second node is received and executed. Alternatively, the transmission circuitry transmits the second node before the first node, in which case the execution unit holds the operand(s) transmitted with the second node until the first node is received and executed.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.